In the fabrication of semiconductor devices, such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers (“wafers”). The wafers (or substrates) include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines and vias are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Patterned conductive layers are insulated from other conductive layers by dielectric materials.
During the series of manufacturing operations, the wafer surface is exposed to various types of contaminants. Essentially any material present in a manufacturing operation is a potential source of contamination. For example, sources of contamination may include process gases, chemicals, deposition materials, and liquids, among others. The various contaminants may deposit on the wafer surface in particulate form. If the particulate contamination is not removed, the devices within the vicinity of the contamination will likely not operate as desired. Because the size of particulate contamination that would cause the failure of devices is on the order of the critical dimension size of features fabricated on the wafer (or greater), removal of small particulate contamination without damaging the features on the wafer can be quite difficult for advanced technology nodes with fine feature sizes.
Conventional wafer cleaning methods have relied heavily on mechanical force to remove particulate contamination from the wafer surface. As feature sizes continue to decrease and become more fragile, the probability of feature damage due to application of mechanical forces on the wafer surface increases. For example, fine features having high aspect ratios are vulnerable to toppling or breaking when impacted by a sufficient mechanical force. To further complicate the cleaning problem, the move toward reduced feature sizes also causes a reduction in the tolerable size of particulate contamination. Particulate contamination of sufficiently small size can find its way into difficult to reach areas on the wafer surface, such as in a trench surrounded by high aspect ratio features. Thus, efficient and damage-free removal of contaminants during modem semiconductor fabrication represents a continuing challenge to be met by advanced wafer cleaning technology. It should be appreciated that the manufacturing operations for flat panel displays also suffer from the same shortcomings of the integrated circuit manufacturing discussed above.
In view of the forgoing, there is a need for materials, apparatus and methods of cleaning patterned wafers that are effective in removing contaminants without damage of the features on the patterned wafers.